\relax \citation{Dira}\citation{Ben1}\citation{Fred}\citation{Toff}\@writefile{toc}{\contentsline {section}{\numberline {1}Background}{3}}\citation{Beni}\citation{Pere}\citation{Feyn}\citation{Mar1}\citation{Slea}\citation{Bar2}\citation{Cira}\citation{Chua1}\citation{Yama}\citation{Lloy}\citation{Reck}\citation{Deut}\citation{DJ}\citation{BB2}\citation{simon}\citation{BV}\citation{Shor}\citation{RMP}\citation{Bras}\citation{Deu2}\citation{Schu1}\citation{JS94}\citation{BV}\citation{Yao}\citation{Deu2}\citation{Divi}\citation{Bar}\citation{Llo2}\citation{Deu3}\citation{Chau}\citation{Copp}\citation{Slea}\citation{Bert2}\citation{Unr}\citation{Chua}\citation{RL}\@writefile{toc}{\contentsline {section}{\numberline {2}Introduction}{7}}\citation{Toff}\citation{Deu3}\citation{Bar}\citation{foot1}\citation{Cop2}\citation{Toff}\citation{Toff}\citation{Clev}\citation{BenO}\citation{Feyn}\@writefile{toc}{\contentsline {section}{\numberline {3}Notation}{9}}\citation{foot2}\citation{Deu2}\@writefile{toc}{\contentsline {section}{\numberline {4}Matrix Properties}{10}}\citation{Expl}\@writefile{toc}{\contentsline {section}{\numberline {5}Two-Bit Networks}{13}}\@writefile{toc}{\contentsline {subsection}{\numberline {5.1}Simulation of General $\wedge _1(U)$ Gates}{13}}\citation{Expl}\citation{Deu2}\@writefile{toc}{\contentsline {subsection}{\numberline {5.2}Special Cases}{14}}\@writefile{toc}{\contentsline {section}{\numberline {6}Three-Bit Networks}{17}}\@writefile{toc}{\contentsline {subsection}{\numberline {6.1}Simulation of General $\wedge _2(U)$ Gates}{17}}\citation{Toff}\citation{Smol}\@writefile{toc}{\contentsline {subsection}{\numberline {6.2}Three-bit gates congruent to $\wedge _2(U)$}{19}}\@writefile{toc}{\contentsline {section}{\numberline {7}$n$-Bit Networks}{20}}\@writefile{toc}{\contentsline {subsection}{\numberline {7.1}Linear Simulation of $\wedge _{n-2}(\sigma _x)$ Gates on $n$-Bit Networks}{22}}\citation{BenO}\citation{Clev}\@writefile{toc}{\contentsline {subsection}{\numberline {7.2}Quadratic Simulation of General $\wedge _{n-1}(U)$ Gates on $n$-Bit Networks}{25}}\@writefile{toc}{\contentsline {subsection}{\numberline {7.3}Linear Approximate Simulation of General $\wedge _{n-1}(U)$ Gates on $n$-Bit Networks}{27}}\citation{Copp}\@writefile{toc}{\contentsline {subsection}{\numberline {7.4}Linear Simulation in Special Cases}{29}}\@writefile{toc}{\contentsline {subsection}{\numberline {7.5}Linear Simulation of General $\wedge _{n-2}(U)$ Gates on $n$-Bit Networks With One Bit Fixed}{30}}\citation{Smol}\@writefile{toc}{\contentsline {section}{\numberline {8}Efficient general gate constructions}{31}}\citation{Reck}\citation{Reck}\bibcite{Dira}{1}\bibcite{Ben1}{2}\bibcite{Fred}{3}\bibcite{Toff}{4}\bibcite{Beni}{5}\bibcite{Pere}{6}\bibcite{Feyn}{7}\bibcite{Mar1}{8}\bibcite{Slea}{9}\bibcite{Bar2}{10}\bibcite{Cira}{11}\bibcite{Chua1}{12}\bibcite{Yama}{13}\bibcite{Lloy}{14}\bibcite{Reck}{15}\bibcite{Deut}{16}\bibcite{DJ}{17}\bibcite{BB2}{18}\bibcite{simon}{19}\bibcite{BV}{20}\bibcite{Shor}{21}\bibcite{RMP}{22}\bibcite{Bras}{23}\bibcite{Deu2}{24}\bibcite{Schu1}{25}\bibcite{JS94}{26}\bibcite{Yao}{27}\bibcite{Divi}{28}\bibcite{Bar}{29}\bibcite{Llo2}{30}\bibcite{Deu3}{31}\bibcite{Chau}{32}\bibcite{Copp}{33}\bibcite{Bert2}{34}\bibcite{Unr}{35}\bibcite{Chua}{36}\bibcite{RL}{37}\bibcite{foot1}{38}\bibcite{Cop2}{39}\bibcite{Clev}{40}\bibcite{BenO}{41}\bibcite{foot2}{42}\bibcite{Expl}{43}\bibcite{Smol}{44}